StarRCTM Custom: Next-Generation Modeling and Extraction Solution for Custom IC Designs

IC design is facing significant challenges beyond the 40-nm process technology node because of increased process variation and its impact on circuit behavior and performance. At advanced process nodes, the increasing number of layers and new device structures result in hundreds of new parameters and many new parasitic effects, which require higher levels of accuracy in modeling and parasitic extraction for simulation and signoff analysis. Custom digital, analog/mixed-signal, and memory designs are particularly sensitive to the nanometer device parameters and parasitics. At 40-nm process technology and beyond, approximating or ignoring the new interconnect and device effects in custom designs can lead to inaccurate post-layout simulation results and jeopardize the chances of successful silicon. The Synopsys StarRCTM Custom extraction solution offers a wide range of features including advanced interconnect and device parasitic modeling and extraction that enable increased signoff accuracy and productivity for today’s system-onchip (SoC) custom IC designs.